1. Field of the Invention
The present invention relates to a drive circuit and a plasma display device.
2. Description of the Related Art
In an AC-driven type plasma display panel (Plasma Display Panel: PDP) which is one of plasma display devices, there are two-electrode type PDPs which perform selective discharge (address discharge) and sustain discharge with two electrodes, and three-electrode type PDPs which perform address discharge by using a third electrode. In the above-described three-electrode type PDPs, there are the case in which the third electrode is formed on the substrate on which the first electrode and the second electrode for performing sustain discharge are placed, and the case in which the third electrode is formed on another substrate opposite to the substrate.
Since each of the above described types of PDP devices is based on the same operation principle, the constitution example of the PDP device in which first and second electrodes which perform the sustain discharge are provided on a first substrate, and a third electrode is separately provided on a second substrate opposite to the first substrate will be explained hereinafter.
FIG. 13 is a diagram showing an entire constitution of an AC-driven type PDP device. In FIG. 13, an AC-driven type PDP device 1 includes a panel P having a plurality of cells disposed in a matrix form with each cell being as one pixel of a display image. More specifically, a cell Cmn which is in the m-th column and the n-th row of the matrix, as shown in FIG. 13. The AC-driven type PDP device 1 is provided with scanning electrodes Y1 to Yn parallel to each other and common electrodes X formed on a first substrate, and address electrodes A1 to Am formed on a second substrate opposite to the above-described first electrode so as to be in a perpendicular direction to the electrodes Y1 to Yn and X. The common electrodes X are disposed close to the respective corresponding scanning electrodes Y1 to Yn, and are commonly connected to each other at one terminal.
The common terminal of the above-described common electrodes X are connected to an output terminal of an X-side circuit 2, and the scanning electrodes Y1 to Yn are connected to output terminals of a Y-side circuit 3. The address electrodes A1 to Am are connected to output terminals of an address side circuit 4. The X-side circuit 2 is constituted of a circuit that repeats a discharge, and the Y-side circuit 3 is constituted of a circuit that performs line-sequential scan and a circuit that repeats a discharge. The address-side circuit 4 is constituted of a circuit that selects a line to be displayed.
These X-side circuit 2, Y-side circuit 3 and address-side circuit 4 are controlled with control signals supplied from a drive control circuit 5. Namely, the address-side circuit 4 and the circuit for performing line-sequential scan inside the Y-side circuit 3 determine which cells are to be lit, and the display operation of the PDP device is performed by repeating discharges of the X-side circuit 2 and the Y-side circuit 3.
The drive control circuit 5 generates the above-described control signals on the basis of display data D from an outside, a clock CLK representing read timing for the display data D, a horizontal synch signal HS and a vertical synch signal VS, and supplies the control signals to the X-side circuit 2, the Y-side circuit 3 and the address-side circuit 4. According to the constitution shown above, the AC-driven type PDP device 1 controls flashing of each cell and can display an image on the Panel P.
Here, a structure of each cell of the AC-driven type PDP device 1 shown in FIG. 13 will be explained. FIGS. 14A to 14C are diagrams showing the structure of the cell included in the AC-driven type PDP device 1 shown in FIG. 13. FIG. 14A is a diagram showing a cross-sectional constitution of a cell Cij as one pixel, which is in the i-th row and the j-th column. In FIG. 14A, a common electrode X and a scanning electrode Yi are formed on a front glass substrate 11. This is coated with a dielectric layer 12 for insulating the electrodes from a discharge space 17, and the resultant structure is further coated with an MgO (magnesium oxide) protective film 13.
Meanwhile, an address electrode Aj is formed on a back glass substrate 14 disposed opposite to the front glass substrate 11, and the address electrode Aj is coated with a dielectric layer 15. The dielectric layer 15 is coated with fluorescent substances 18. The discharge space 17 between the MgO protective film 13 and the dielectric layer 15 is charged with Ne+Xe Penning gas or the like.
FIG. 14B is a diagram for explaining a capacitance Cp of the AC-driven type PDP device. As shown in FIG. 14B, in the AC-driven type PDP device, capacitance components Ca, Cb and Cc exist in the discharge space 17, between the common and scanning electrodes X and Y, and in the front glass substrate 11, respectively, and the capacitance Cp cell per cell (Cp cell=Ca+Cb+Cc) is determined by the sum of them. The total of the capacitances Cp cell of all cells is the panel capacitance Cp.
FIG. 14C is a diagram for explaining light emission of the AC-driven type PDP device. As shown in FIG. 14C, the fluorescent substances 18 of red, blue and green are applied to be arranged in each color in stripes onto an inner surface of a rib 16. The fluorescent substances 18 are excited by a discharge between the common and scanning electrodes X and Y to emit a light 19.
Next, an operation of the AC-driven PDP device 1 shown in FIG. 13 will be explained by using a waveform diagram.
FIG. 15 is a waveform diagram showing the operation of the AC-driven type PDP device 1 shown in FIG. 13. FIG. 15 shows an example of waveforms of voltage which is applied to the X, Y and address electrodes in one subfield out of a plurality of subfields constituting one frame. One subfield is divided into a reset period constituted of a full writing period and a full erasing period, an address period, and a sustain discharge (sustain) period.
First, in the reset period, the voltage applied to the common electrodes X is lowered to (−Vs/2) from the ground level. On the other hand, as for the voltage applied to the scanning electrodes Y, the voltage which is the resultant voltage of adding up the voltage Vw and the voltage (Vs/2) is applied to the scanning electrodes Y. At this time, the voltage (Vs/2+Vw) gradually rises with a lapse of time. As a result, the potential difference between the common electrodes X and the scanning electrodes Y becomes (Vs+Vw), and discharge occurs in every cell of every display line to generate wall charges, irrespective of the preceding display state (full writing).
Next, after the voltage of the common electrodes X and the scanning electrodes Y is returned to the ground level, the applied voltage to the common electrodes X is raised to (Vs/2) from the ground level, and the applied voltage to the scanning electrodes Y is dropped to (−Vs/2). As a result, the voltage by the wall charges themselves exceeds the discharge start voltage in every cell, and discharge is started. At this time, the stored wall charges are erased by the applied voltage to the common electrodes X as described above (full erasing).
Next, in the address period, address discharge is line-sequentially performed to turn each cell ON/OFF in accordance with the display data. At this time, a voltage (Vs/2) is applied to the common electrodes X. When a voltage is applied to the scanning electrode Y corresponding to a certain display line, the voltage at a level of (−V2/2) is applied to the scanning electrodes Y that are selected line-sequentially, and the voltage at the ground level is applied to the scanning electrode Y that are not selected.
At this time, an address pulse having a voltage Va is selectively applied to an address electrode Aj corresponding to a cell to undergo sustain discharge, that is, to be turned ON, in the address electrodes A1 to Am. As a result, discharge occurs between the address electrode Aj to be turned ON and the scanning electrode Y that is selected line-sequentially. With this being as priming (pilot), discharge between the common electrodes X and the scanning electrodes Y starts immediately. Wall charges in such an amount as to enable the next sustain discharge are stored on the surface of the MgO protective film on the common electrode X and the scanning electrode Y of the selected cell.
Thereafter, in the sustain discharge period, the voltage of the common electrodes X gradually rises by the operation of the power recovering circuit which will be described later. Subsequently, in the vicinity of the peak of the rise, the voltage of the common electrodes X is clamped to (Vs/2).
Next, the voltage of the scanning electrodes Y gradually drops. At this time, the power recovering circuit recovers part of the charges. The operation of the power recovering circuit will be described later. In the vicinity of the peak of the drop, the voltage of the scanning electrodes Y is clamped to (−V2/2). Similarly, when the applied voltage to the common electrodes X and the scanning electrodes Y is raised to the ground level (0V) from the voltage (−Vs/2), the applied voltage is gradually raised. In the scanning electrodes Y, the voltage (Vs/2+Vx) is applied only when high voltage is applied initially. The voltage Vx is the added voltage to generate necessary voltage for sustain discharge, which is the addition of the voltage of the wall charges generated in the address period shown in FIG. 15.
When the applied voltage to the common electrodes X and the scanning electrodes Y is lowered to the ground level (0V) from the voltage (Vs/2), the applied voltage is gradually lowered and part of the charges stored in the cells is recovered into the power recovering circuit.
Thus, in the sustain discharge period, the voltages (+Vs/2, −Vs/2) differing in polarity from each other are alternately applied to the common electrodes and the scanning electrode Y in each display line to perform sustain discharge, and an image of one subfield is displayed. The operation of alternate application is called a sustain operation, and the detailed operation will be explained by using FIG. 18 that will be described later.
In each cell of the AC-driven type PDP device, the capacitance components exist in the discharge space of each cell, between the common and scanning electrodes X and Y, and in the front glass substrate, respectively, and the capacitance per one cell is determined by the total of them. The fluorescent substances of red, blue and green are applied to be arranged in each color in stripes onto inner surfaces of the cells of the AC-driven PDP device. The fluorescent substances are excited by the discharge between the common and scanning electrodes X and Y to emit light.
However, the aforementioned X-side circuit 2 and the Y-side circuit 3 (hereinafter, called drive circuits) are circuits for outputting signals at high voltage to cause discharge inside the cells, and therefore each element constituting the drive circuits is required high voltage resistance, which causes an increase in the manufacturing cost. Thus, there is proposed the art of simplifying the circuit constitution and reducing the manufacturing cost by reducing the withstand voltage of each element included in the aforesaid drive circuits. There is proposed a drive circuit which performs discharge between the electrodes by utilizing the potential difference between the electrodes, for example, by applying a positive voltage to one electrode and a negative voltage to the other electrode (for example, the following Patent Document 1). This circuit is called a TERES (Technology of Reciprocal Sustainer) circuit.
A schematic constitution and an operation of the aforementioned TERES circuit will be explained hereinafter.
FIG. 16 is a diagram showing a schematic constitution of a drive circuit of the AC-driven type PDP device 1 shown in FIG. 13 (only the X-side circuit 2 is shown, the Y-side circuit 3 is omitted because it has the same constitution and operation).
In FIG. 16, a capacitive load 20 (hereinafter, called “load”) is the total capacitance of the cell Cmn formed between one common electrode X and one scanning electrode Y. The common electrode X and the scanning electrode Y are formed in the load 20. Here, the scanning electrode Y means an optional scanning electrode in a plurality of scanning electrodes Y1 to Yn.
First, in the common electrode X side, switches SW1 and SW2 are connected in series between a power supply line (power source line) of the voltage (Vs/2) supplied from a power source and the ground (GND). One terminal of a capacitor C1 is connected to an interconnection point of the above-described two switches SW1 and SW2, and a switch SW3 is connected between the other terminal of the capacitor C1 and the ground. A signal line connected to the one terminal of the capacitor C1 is set as a first signal line OUTA, and a signal line connected to the other terminal is set as a second signal line OUTB.
Switches SW4 and SW5 are connected in series to both terminals of the above-described capacitor C1. An interconnection point of the two switches SW4 and SW5 is connected to the common electrode X of the load 20 via an output line OUTC, and is also connected to a power recovering circuit 21. The power recovering circuit 21 includes two coils L1 and L2 connected to the load 20, a switch SW6 connected in series to the one coil L1, and a switch SW7 connected in series to the other coil L2. Further, the power recovering circuit 21 includes a capacitor C2 connected between an interconnection point of the above-described two switches SW6 and SW7 and the second signal line OUTB.
A two-system series resonant circuit is constructed by the above-described capacitive load 20 and the respective coils L1 and L2 connected to the capacitance load 20. Namely, this power recovering circuit 21 has a two-system L-C resonant circuit, and recovers the charges, which are supplied to the panel P by the resonance of the coil L1 and the load 20, by the resonance of the coil L2 and the load 20.
The aforementioned switches SW1 to SW7 are controlled by control signals respectively supplied from the drive control circuit 5 shown in FIG. 13. As described above, the drive control circuit 5 is constituted by using a logical circuit and the like, generates the above-described control signals on the basis of the display data D supplied from the outside, the clock CLK, the horizontal synch signal HS, the vertical sync signal VS and the like, and supplies the control signals to the switches SW1 to SW7. As described above, the period in which the common electrode X and the scanning electrode Y in the cell discharge is called the sustain discharge period.
FIG. 18 is a time chart showing a driving waveform of the sustain discharge period by the drive circuit of the AC-driven type PDP device 1 constituted as in the above-described FIG. 16.
In the sustain discharge period, in the common electrode X side, the switches SW1, SW3 and SW5 are turned on first, and the remaining switches SW2, SW4, SW6 and SW7 are turned OFF. At this time, the voltage of the first signal line OUTA (first potential) becomes (+Vs/2), and the voltage of the second signal line OUTB (second potential) and the voltage of the output line OUTC become the ground level (t1).
Next, by turning ON the switch SW6 in the power recovering circuit 21, L-C resonance occurs with the coil L1 and the capacitance of the load 20, and the charges recovered in the capacitor C2 is supplied to the load 20 via the switch SW6 and the coil L1 (t2). By such a flow of the current, the voltage of the output line OUTC which is applied to the common electrode X gradually rises as shown in the times t2 to t3 in FIG. 18. The switch SW5 is turned OFF at the time t2.
Next, by turning ON the switch SW4 in the vicinity of the peak voltage occurring at the resonance time, the voltage of the output line OUTC which is applied to the common electrode X is clamped to (Vs/2) (t3). At the time t3, the switch SW6 is turned OFF.
When the voltage of the output line OUTC which is applied to the common electrode X is lowered to the ground level (0V) from (Vs/2), the switch SW7 is turned ON first, and the switch SW4 is turned OFF (t4). As a result, the L-C resonance occurs with the coil L2 and the capacitance of the load 20, and part of the charges stored in the load 20 is recovered into the capacitor C2 in the power recovering circuit 21 via the coil L2 and the switch SW7. By such a flow of the current, the voltage of the output line OUTC which is applied to the common electrode X gradually lowers as shown in the times t4 to t5 in FIG. 18.
Next, by turning ON the switch SW5 in the vicinity of the peak voltage (peak in the minus direction) which occurs at the resonance time, the voltage of the output line OUTC which is applied to the common voltage X is clamped to (−Vs/2) (t5). The switch SW7 is turned OFF at the time t5.
Next, the switches SW1, SW3 and SW5 are turned OFF, and the switches SW2 and SW4 are turned ON. At this time, the switches SW6 and SW7 are kept OFF. As a result, the voltage of the first signal line OUTA becomes the ground level, and the voltage of the second signal line OUTB and the output line OUTC becomes (−Vs/2) (t6).
Next, by turning ON the switch SW7 in the power recovering circuit 21, the L-C resonance occurs with the coil L2 and the capacitance of the load 20, and the charges (minus side) recovered in the capacitor C2 are supplied to the load 20 via the switch SW7 and the coil L2 (t7). By such a flow of the current, the voltage of the output line OUTC, which is applied to the common electrode X, gradually lowers as shown in the times t7 to t8 in FIG. 18. The switch SW4 is turned OFF at the time t7.
Next, by turning ON the switch SW5 in the vicinity of the peak voltage (peak in the minus direction) which occurs in this resonance time, the voltage of the output line OUTC which is applied to the common electrode X is clamped to (−Vs/2) (t8). At the time t8, the switch SW7 is turned OFF.
When the voltage of the output line OUTC, which is applied to the common electrode X, is raised to the ground level (0V) from (−Vs/2), the switch SW6 is turned ON first, and the switch SW5 is turned OFF (t9). As a result, the L-C resonance occurs with the coil L1 and the capacitance of the load 20, and part of the charges stored in the load 20 is recovered into the capacitor C2 inside the power recovering circuit 21 via the coil L1 and the switch SW6. By such a flow of the current, the voltage of the output line OUTC that is applied to the common electrode X gradually rises as shown in the times t9 to t10 in FIG. 18.
Next, by turning ON the switch SW4 in the vicinity of the peak voltage that occurs at the time of the resonance, the voltage of the output line OUTC, which is applied to the common electrode X, is clamped to the ground level (t10). The switch SW6 is turned OFF at the time t10. By the operation as described above, the drive circuit shown in FIG. 16 applies the voltage, which changes from −Vs/2 to Vs/2, to the common electrode X during the sustain discharge period. The voltage (+Vs/2, −Vs/2) with a different polarity from the voltage which is supplied to the aforementioned common electrode X is alternately applied to the scanning electrode Y in each display line. From the above, the AC-driven type PDP device 1 can perform sustain discharge.
During the sustain discharge period, wall charges with a different polarity in such an amount as makes the sustain discharge possible are stored on the protective film surface on the common electrode X and the scanning electrode Y. When discharge is carried out between the common electrode X and the scanning electrode Y, the wall charges on the common electrode X and the scanning electrode Y in the cell become the wall charges with the reverse polarity from the polarity the wall charges had so far, and converge the discharge. At this time, a time is required for the wall charges to move, and the time is determined by the time during which the voltage +Vs/2 or the voltage −Vs/2 is applied to the common electrode X.
As a specific example of the circuit shown in FIG. 16, a circuit in FIG. 17 can be conceived. FIG. 17 shows a circuit diagram in which a power MOSFET (or IGBT may be used) is used as each of the switch elements SW1 to SW5 in the circuit shown in FIG. 16. In FIG. 17, drive circuits which drive the respective switch elements SW1 to SW5 are also shown. In FIG. 17, drive circuits M1, M2, M3N and M3P are constituted by using drive circuits MA. The drive circuit MA is constituted by using a waveform processing circuit 802, a high level shift circuit 803 and an output amplifying circuit 804.
A signal IN1 that is inputted from an input signal terminal is converted into a signal with the voltage of an output reference voltage terminal Vss as a reference, via the high level shift circuit 803. The output voltage of the high level shift circuit 803 is amplified via the output amplifying circuit 804, and is supplied to the switch element SW1 as drive pulse for the switch element SW1. Power supply voltage of the output amplifying circuit 804 is supplied to an output power supply terminal Vc of the drive circuit M1 via a diode DE from a power supply voltage Ve. In the period in which the first signal line OUTA has the ground voltage (the period in which the switch element SW2 is ON, t6 to t10 in FIG. 18), the above-described diode DE is turned ON, and the charges are charged in a capacitor CE. The charges are supplied as the drive pulse to a control terminal of the switch element SW1 via the above-described output amplifying circuit 804 in the period from t1 to t6 (the same timing of the next cycle) in FIG. 18.
In FIG. 17, drive circuits M4, M5, M6 and M7 are constituted by using drive circuits MB. The drive circuit MB is constituted by using a gate coupler that is an optical transmitting element. The gate coupler is an element in which both a photo coupler and an amplifying circuit are contained in one package, and is capable of directly driving gate terminals of a power MOSFET, IGBT and the like. Instead of the gate coupler, the combination of a photo coupler and an amplifying circuit may be used.
By works of the above-described gate-couplers M4 to M7, the switches SW4 to SW7 can be driven based on input signals IN4 to IN7 which are inputted from the input terminals with the ground voltage as the reference. In the above-described drive circuit MB, an input part and an output part are separated by light, and therefore stable drive can be performed even if the reference voltages of the input part and the output part differ. The driving method of the TERES circuit using an optical transmitting element is described in the following Patent Document 2.                [Patent Document 1] EP Patent Application Publication No. 1065650 (Japanese Patent No. 3201603)        [Patent Document 2] US Patent Application Publication No. 2002-0097203 (Japanese Patent Application Laid-open No. 2002-215087)        